The present invention relates to a method of manufacturing a semiconductor device including a step of patterning a conductor layer, which is particularly applicable to a MOS transistor and, more particularly, to a technique for patterning a conductor layer when a difference between the etching rates of the conductor layer to be etched and an underlying layer is not sufficiently large.
With a recent tendency toward greater miniaturization of semiconductor devices, anisotropic etching in which etching progresses substantially vertically with respect to the semiconductor wafer surface is widely adopted in the manufacture of semiconductors, as described in pp. 300-302 of "SEMICONDUCTOR HANDBOOK REVISED EDITION (1977)". Reactive ion etching is a typical anisotropic etching method, and is suitable for miniaturization. However, reactive ion etching does not assure a sufficient difference between the etch rates of a film to be etched and an underlying film.
FIGS. 1A to 1C are sectional views showing the steps of a method for manufacturing a MOS transistor with an Al gate by the conventional method.
Referring to FIG. 1A, a pair of n.sup.+ -type regions 12 and 13 with a predetermined distance therebetween are formed in the surface layer of a p-type silicon semiconductor substrate 11. A thick silicon oxide film 14 about 5,000 to 6,000 .ANG. thick is formed on the surface of the substrate 11 by the CVD (chemical vapour deposition) method. A thin silicon oxide film 16 for the gate having a thickness of about 700 .ANG. is also formed on the substrate 11 by thermal oxidation. The element formation region of the substrate 11 is subjected to ion-implantation and annealing for control of the threshold voltage as needed. Contact holes 17 and 18 corresponding to the n.sup.+ -type regions 12 and 13 are formed in the thick silicon oxide film 14.
A conductor layer 19 having thickness of about 6,000 to 7,000 .ANG. and consisting of a mixture of 1% by weight of silicon and aluminum is formed on the thick and thin silicon oxide films 14 and 16. A resist film 20 of a redetermined thickness is formed on the conductor layer 19 and is patterned to have a predetermined shape.
Subsequently, the conductor layer 19 is selectively etched by reactive ion etching using the patterned resist film 20 as a mask, as shown in FIG. 1B, until the exposed portions of the conductor layer 19 are removed from the thin silicon oxide film 16.
Thereafter, the resist film 20 is removed. Using the gate structure formed on the thin silicon oxide film 16 as a mask, an n-type impurity is ion-implanted, as shown in FIG. 1C, to form n.sup.+ -type regions 12' and 13' in self-alignment with the n.sup.+ -type regions 12 and 13. Source and drain regions are thus formed.
In the manufacturing steps as described above, when the conductor layer 19 is formed as shown in FIG. 1A, a step is formed between the thick silicon oxide film 14 and the thin silicon oxide film 16. Then, when the conductor layer 19 is later etched, a corresponding step remains at the portion of the conductor layer 19 corresponding to this step. FIG. 2 is an enlarged sectional view of the gate region of the structure shown in FIG. 1A. When a thickness T1 of the portion of the conductor layer 19 which corresponds to the step is about 1.2 .mu.m, the conductor layer 19 other than this portion will have a thickness T2 of 0.6 .mu.m, which is half of T1. Then, the etching time of the conductor layer 19 must be long enough to completely etch the conductor layer 19 including the thick portion thereof.
If the etch rate of the conductor layer 19 is 1,000 .ANG./min, the etching time for completely removing the conductor layer 19 at the gate region is calculated to be 1.2 .mu.m.div.1,000 .ANG./min=12 minutes. However, since the thickness of the conductor layer 19 on the thin silicon oxide film 16 is 0.6 .mu.m, which is half that at the step portion thereof, 12-minutes etching results in the etching of the underlying silicon oxide film 16 as well. If the etch rate of the thin silicon oxide film 16 is 10 times less than that of the conductor layer 19, the thickness of the film 16 is reduced by 600 .ANG.. Furthermore, since the original thickness of the thin silicon oxide film 16 is 700 .ANG., overetching to allow a further margin results in almost no silicon oxide film 16 remaining, as shown in FIG. 1C. This significantly degrades the switching characteristics and reliability of the manufactured MOS transistor.
Meanwhile, methods have been proposed by Y. Homma et al., (J. Electrochem. Soc., 126, pp. 1531-1532 (1979)) and by A. C. Adams & C. D. Capio (J. Electrochem. Soc., 128, pp. 423-429 (1981)). According to these methods, an organic resist is coated on a wafer surface having a three-dimensional pattern, in order to provide a level surface. Thereafter, the wafer surface layer is etched under conditions such that the etch rates of the three-dimensional pattern and the resist film are the same, thereby allowing even or level etching of the wafer surface. However, these methods only allow level etching of the wafer surface and may not provide a solution to the problem of a decrease in the film thickness of the underlying film during etching of the desired film.